1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device. More particularly, the present invention relates to a method for forming a shallow trench isolation (STI) of a semiconductor device.
2. Description of the Relation Art
An isolation region is formed in an integrated circuit for preventing a short circuit from occurring between adjacent device regions on a substrate. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions on semiconductor device. However, since internal stress is generated and bird's beak encroachment occurs in the isolation structures, LOCOS cannot effectively isolate devices.
The shallow trench isolation (STI) technique has been developed to improve the bird's beak encroachment of the LOCOS so as to achieve an effective isolation structure. Typically, the STI process comprises the steps of using a mask to define and pattern a shallow trench on a substrate by anisotropic etching process, and then filling he shallow trench with oxide for use as a device isolation structure.
FIGS. 1A through 1E are schematic, cross-sectional views showing the progression of the conventional manufacturing steps for a shallow trench isolation structure. Referring to FIG. 1A, a pad oxide layer 102 is formed by thermal oxidation on a substrate 100. The pad oxide layer 102 is used to protect the substrate 100 surface during the whole processes. A silicon nitride layer 104 as a mask layer is formed by low pressure chemical vapor deposition (LPCVD) on the pad oxide layer 102.
Referring to FIG. 1B, a photoresist layer is formed on the silicon nitride layer 104, after which a portion of the silicon nitride layer 104, the pad oxide layer 102 and the substrate 100 are removed by etching to form a trench 112 within the substrate 100 and expose the substrate 100. Then, the photoresist layer is removed from the silicon nitride layer 104.
Referring to FIG. 1C, a liner layer 114 is formed by high temperature thermal oxidation on the trench 112 surface. The liner layer 114 extends to a top corner 140 of the trench 112 and connects with the pad oxide layer 102. An insulation layer 116 is deposited by atmospheric pressure chemical vapor deposition (APCVD) with tetra-ethyl-ortho-silicate (TEOS) as a gas source over the silicon nitride layer 104 and within the trench 112. The insulation layer 116 is made of silicon oxide. A densification step is subsequently performed on the insulation layer 116 at high temperature.
Referring to FIG. 1D, the silicon nitride layer 104 is used as a polishing stop layer, and a portion of the insulation layer 116 above the surface of the silicon nitride layer 104 is removed by chemical mechanical polishing (CMP) to form an insulation layer 116a and expose the silicon nitride layer 104. A surface of the insulation layer 116a surface is level with a surface of the silicon nitride layer 104.
Referring to FIG. 1E, the silicon nitride layer 104 is removed by using a hot phosphoric acid (H.sub.3 PO.sub.4) to expose the pad oxide layer 102. The pad oxide layer 102 is removed by using hydrogen fluoride (HF) to form a shallow trench isolation structure 117.
The pad oxide layer 102 is removed by isotropic etching, using hydrogen fluoride (HF); however, the isotropic etching has a tendency to etch laterally. After performing the isotropic etching process, a recess 150 occurs, in the top corner 140 (FIG. 1C) of the trench 112 because insulation layer 116a covers the top corner 140 of the trench 112. The recess 105 leads to a kink effect, and the kink effect causes a threshold voltage reduction and leads to generation of a leakage current while forming the corner parasitic MOSFET.